The present invention relates to an input/output device which transfers data between semiconductor devices and more particularly to an input/output device which allows a multi-bit input/output operation. More specifically, the present invention relates to an output device which allows a multi-bit output operation, an input device that corresponds to the output device, an input/output apparatus which comprises the output device and the input device, and an input/output operation method.
Today, with the advance of fine processing technology for semiconductor devices, ultra large-scale integration chips containing several millions of transistors, such as high-speed 32- and 64-bit MPUs, and 16- and 64-Mbit DRAMs are being produced. The operating frequency of MPUs has been increased up to 200 MHz. Further, the bus carrying data between an MPU and memory is being increased in width and available in 32, 64, and 128 bits.
With increasing MPU operating frequency, the operating frequency (data rate) of data bus is increased to 60 and 100 Mb/s per pin. The age of 64.times.100 Mb/s=6.4 Gb/s for the whole bus is also drawing near. In such a state, a large amount of current will flow through the entire output circuit and the oscillation of power lines due to parasitic capacitance associated with the power lines will become very great. For this reason, some measures must be taken to avoid malfunctions.
FIG. 1 shows a conventional input/output circuit of multi-bit (16 bits) configuration. Internal data of 64 bits from an input buffer is taken into an output buffer. The output buffer operates synchronously with the input buffer to output the data onto a 64-bit-wide bus. An input buffer in another chip receives the data over the bus. Since each bit in the output is produced at the same time, the width of the bus becomes large. When the number of bus data lines to be switched at the same time increases, the oscillation of power lines (Vcc, Vss) due to parasitic inductance associated with the power lines becomes serious.
In the case of the output buffer, when its output changed from a high level to a low level, the power supply voltages Vcc and Vss temporarily lowers greatly and then fluctuates in the opposite direction due to the parasitic inductance. This oscillation is repeated with the power supply Vcc being decayed gradually. In particular, when all the I/O lines are switched in the same direction, for example, when all the I/O lines go from a high level to a low level, the oscillation of the power supply voltages becomes maximum. In this case, the oscillation becomes in-phase noise in which Vcc and Vss fluctuate in the same direction. When each bit, except one bit, is the same data, a large oscillation of signal voltage will occur on the bit line corresponding to the data that is opposite to that on the other bit lines.
FIGS. 2A and 2B show examples of conventional output devices in terms of an output buffer circuit for one bit and its associated power supply and output lines. When there are many output lines, I/O lines are usually used which are in common to input lines. In this example, only the output buffer is shown with the input buffer omitted. In many cases each of the output buffers is associated with four I/O lines and one power supply line (Vcc) and one ground line (Vss) and connected from a chip to a printed circuit board external to a package containing the chip through a bonding wire and a lead frame of the package. That is, charging and discharging currents on the four I/O lines flow into the printed circuit board through the two Vcc and Vss lines.
Even with a large number of Vss and Vcc pins placed, however, the power supply lines oscillate greatly due to the parasitic inductance (L1 and L2 in FIG. 2A) associated with the bonding wire and the lead frame. The parasitic inductance per pin is usually in the range of several nanohenries to tens of nanohenries.
The output line is also associated with parasitic capacitance on the bonding wire and the lead frame within the package and the printed circuit board wire. In this case, however, the I/O line oscillation (ringing) or reflections can be suppressed by matching the characteristic impedance (Zo=(L/C)) to the terminating resistance Rt. However, the ringing component on the I/O line resulting from the parasitic inductance associated with the power supply lines will remain. Compared to the conventional LVTTL compatible interface, the new interfacing technologies, such as terminated LVTTL, CTT, GTL, SSTL, Rambus, etc., is based on a combination of the termination, the impedance matching, and a low-amplitude technique.
However, these technologies will suppress only the influence of the I/O line inductance, but cannot suppress the influence of the power supply inductance. When the power supply line ringing becomes great, the following problems will arise. First, output signals will fluctuate, resulting in failure to make distinction between 0 and 1 in signals on the input side. Second, the power supply fluctuation causes malfunctions in the circuitry within the chip. Third, the chip power supply fluctuation makes it difficult to make distinction between 0 and 1 in signals applied to the chip, failing in correct signal reception.
The way to suppress the power supply fluctuation is to lower the driving capability of the driver at the last stage of the output device or to reduce the peak current by turning the driver ON slowly. If, when the power supply of the output device of FIG. 2A and the power supply of the other portion of the chip are common, the power supply lines fluctuate greatly, the influence of the package inductance will directly be transferred to the internal circuit or the input device, making the first, second and third problems more serious.
One way to solve the second and third problems is to separate the power supply lines (VccQ, VssQ) dedicated to the output device from the other power supply lines (Vcc', Vss') and connect them to the power supply lines (Vcc', Vss') on the printed circuit board through separate pins of the package. In this case, the influence of the parasitic inductance (L1, L2) associated with the bonding wires and the lead frame of the package for the output device can be reduced.
The above way is suitable for the case where the I/O lines are small in number. However, when the number of I/O lines is increased to 32, 64, 128, or 256, the power supply lines (Vcc', Vss') on the printed circuit board (PCB) fluctuate greatly due to the influence of the parasitic inductance on the PCB because a large amount of current flows even if the number of the power supply line pins for the output device is increased. As a result, the power supply lines (Vcc', Vss') for the chip internal circuitry and the input circuit fluctuate through the power supply pins for the other circuitry than the output device. This will result in the second and third problems.
Another conventional approach to solve the above problems is illustrated in FIG. 2B. In this example, two output lines are provided for one bit of data to thereby provide complementary outputs (Dout, /Dout).
In this case, a match occurs between the amount of current flowing from the inside of the chip to the output line and the amount of current flowing from the output line to the inside of the chip. Thus, if a large capacitance (C1 in FIG. 2B) is installed in the chip, most of charge when the output lines are driven is furnished by discharging of the capacitance, resulting in a substantial decrease in current components that flow into and out of the output lines through the parasitic inductances of the power supply lines. Apparently, the current components become zero. In this case, the fluctuation of the power supply lines will contain only a noise component in which Vcc and Vss are 180 degrees out of phase with each other, which is the same as power supply noise when the peak of current dissipation is reached. That is, only a noise component such that, Vcc is lowered, Vss is raised and vice versa is produced. The noise could be further reduced with the use of a larger internal capacitance C1.
Although having an advantage that the power supply noise due to the parasitic inductance associated with the power supply lines can be substantially suppressed, the circuit has a serious disadvantage that the number of output pins, the number of I/O lines, the number of output buffers and the power dissipation are all doubled over the conventional one.
As described above, if, in the conventional output device having a large number of outputs, the output lines are simultaneously driven in the same direction, the peak current increases to make the fluctuation of the power supply lines great. As a result, there arise serious problems that, first, output signals fluctuate to make it impossible to make a distinction between one and zero on the input side, second, malfunctions occur in the chip, and, third, it becomes difficult to decide whether each of signals input to the chip is a 1 or 0.
With the device having a complementary pair of output lines for one bit of data, the noise can be substantially reduced, but the number of output pins, the number of I/O lines, the number of output buffers and the power dissipation are doubled.